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Graphcore

Staff/Principal Logical Design Engineer

Bristol
Posted about 19 hours ago
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About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

Working within the Logical Design team, the Staff/Principal Silicon Logical Design Engineer is responsible for a wide range of logical design tasks which require working closely with other engineers within the Silicon department. This person is responsible for helping the team deliver high quality micro-architecture specifications and RTL for Graphcore chips, and assisting the rest of the Silicon teams to ensure we can meet the company objectives for silicon delivery.

The Team

The Logical Design team sits within the Silicon team. We are responsible for delivering the micro-architecture and RTL design to implement the chip architecture specification for Graphcore Silicon.

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£35,000/yr

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Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Responsibilities and Duties

  • Being part of the Logical Design team, producing high quality micro-architecture specification and RTL for Graphcore chips
  • Ensuring good communication between different teams and across multiple sites
  • Contributing to shared design infrastructure and flows
  • Using EDA tools and the Graphcore design flow to design innovative technologies
  • Contributing to block-level and chip-level checks and auditing (Linting, Synthesis, Timing Closure, CDC, RDC, Coverage)
  • Working closely with Physical Design, Verification and DFT teams

Essential skills:

  • Degree in Computer Science, Engineering or a related subject
  • Digital design experience in a relevant industry
  • Be highly motivated, a self-starter, and a team player
  • Ability to work across teams and finding solutions to problems
  • Ability to solve design issues through programming, e.g. Python, Tcl
  • Strong competency in SystemVerilog or VHDL
  • Knowledge of digital design flows
  • Capable of managing time and priorities

Desirable:

  • Processor design
  • Application specific blocks
  • High-speed serial interfaces
  • Complex third-party IP integration
  • Experience leading teams
  • Arithmetic pipeline design
  • Floating-point design
  • Design for test
  • Synthesis
  • Timing Analysis
  • Logical Equivalence
  • Project Planning
  • Power Integrity
  • Silicon transistor knowledge

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Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

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Skills

SystemVerilog
VHDL
Python
Tcl
Digital Design
RTL Design
Micro-architecture Specification
Synthesis
Timing Closure
CDC
RDC
Linting
DFT
Physical Design
Verification
EDA Tools

Location

Bristol, England, United Kingdom

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