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Application Specific Integrated Circuit Design Engineer

Cambridge
Posted about 22 hours ago
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Role Overview

Due to growth, this is a fantastic opportunity to join a global company in their Cambridge office. The role offers broad ownership across the entire ASIC development cycle, from architecture and RTL design through verification, DFT, implementation, and silicon validation. The role combines challenging mixed-signal design work with the opportunity to provide technical leadership and contribute to design methodology improvements in one of the UK’s leading technology and Semiconductor hubs.

Key Responsibilities

  • Design and develop functional digital blocks and contribute to the delivery of complete mixed-signal ASICs from concept through to full production maturity
  • Support product definition activities through feasibility studies, architecture development, and FPGA-based digital emulation
  • Develop RTL designs in SystemVerilog that meet system performance, functionality, and quality requirements
  • Create comprehensive block-level verification environments and testbenches to validate digital functionality
  • Perform digital synthesis and develop appropriate physical design constraints to achieve power, performance, and area (PPA) targets
  • Generate and maintain high-quality design documentation and actively participate in design reviews
  • Provide technical leadership and mentorship to other team members
  • Drive continuous improvement of digital design methodologies and best practices

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Skills and Expertise

  • Have a minimum of 5 years' experience in digital IC design using standard-cell methodologies
  • Possess deep knowledge of industry-standard digital design methodologies and best practices
  • Demonstrate expertise in fully synthesised digital design flows, including RTL development and logic synthesis
  • Be highly proficient in SystemVerilog and modern digital EDA toolchains
  • Have experience applying timing and physical design constraints within automated place-and-route flows
  • Understand production test requirements and have hands-on experience implementing DFT techniques such as scan-based testing to maximise test coverage
  • Have practical experience with low-power digital design techniques and power optimisation methodologies
  • Be proficient in scripting languages such as TCL and Python

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Benefits

A competitive compensation and benefits package is offered, including joining stock + Employee stock purchase scheme and a base salary.

Contact

Please contact Rachel Mason for more information.

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Skills

ASIC Design
RTL Design
Mixed-signal Design
SystemVerilog
Digital Synthesis
DFT
Silicon Validation
FPGA Emulation
Physical Design
Logic Synthesis
EDA Toolchains
Scan-based Testing
Low-power Design
Tcl
Python
Standard-cell Methodologies

Location

Cambridge, England, United Kingdom

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