European Tech Recruit
CPU Design Verification Engineer

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CPU Design Verification Engineer
European Tech Recruit are working closely with a leading semicon company, based in Cambridge, who are looking for a talented CPU Design Verification Engineer to join their team.
In this role you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end product.
Responsibilities as CPU Design Verification Engineer:
- Working with CPU and SOC Architects to understand the concepts and high-level system requirements.
- Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.
- Developing Verification Methodology, ensuring scalability and portability across environments.
- Developing Verification environment, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
- Developing Verification Plans and Testbenches for your functional domain.
- Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures.
- Tracking and report DV progress using a variety of metrics, including Bugs and Coverage.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Requirements:
- Deep knowledge of Micro-Processor Verification functions and Architectures, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.
- Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.
- Experience in leading a small team of Verification engineers performing CPU Verification.
- Advance techniques such as: Formal, Assertions, and Silicon bring up, is helpful.
- In-depth knowledge of Micro-processor functions, Architectures, and Micro-architectures.
- Experience in writing Test plans, portable Testbenches, Transactors, and Assembly code.
- Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Formal Proof Tools.
- Ability to develop and work independently on a Block/Unit of the design.


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If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com.
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