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CPU Design Verification Engineer - (Cambridge, UK)
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CPU Design Verification Engineer - (Cambridge, UK)
CPU Design Verification Engineer (Senior)
A fantastic opportunity for an experienced Design Verification Engineer to join a global leader in semiconductors, working alongside their CPU Team in Cambridge (UK).
About the Role
As a Senior CPU Verification Engineer, you will:
- Work with Chip Architects to validate concepts of CPU and SOC-level micro-architectures.
- Oversee a selected part of the CPU Design Verification, ensuring functionality meets launch-readiness for the end product.
Responsibilities
- Collaborate with CPU and SOC Architects to:
- Understand concepts and high-level system requirements.
- Develop:
- Detailed Test Plan and Coverage Plans based on architecture and micro-architecture.
- Scalable and portable Verification Methodology.
- Full Verification Environment, including Stimulus, Checkers, Assertions, Trackers, and Coverage.
- Design Verification Plans and Testbenches for your assigned domain.
- Execute verification workflows:
- Design Bring-up and DV environment Bring-up.
- Regressions to enable all features under your care.
- Debug of test failures with thorough analysis.
- Track and report DV progress using metrics like:
- Bug tracking (status/resolution).
- Coverage reporting.
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Requirements
Core Expertise
Deep knowledge of:
- Micro-Processor Verification functions and designs, including:
- Cache Coherence
- Memory ordering & Consistency
- Prefetching
- Branch Prediction
- Renaming
- Speculative Execution
- Address Translation / Memory Management (MMU/TPM)
Technical Skills
- Proficiency in Random Instruction Sequencing (RIS) testing at:
- Block/Unit-level
- Subsystem/Chip-level to validate correctness.
- Team Leadership: Experience managing a small group of Verification Engineers in CPU design projects.
- Familiarity with advanced techniques like:
- Formal Verification
- Silicon Bring-up Methodology
- Utilisation of Assertion-based Debugging.
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Hands-on Experience
- Writing functional Test Plans and modular Testbenches.
- Developing portable Transactors and Assembler/Assembly Code for low-level control.
- Operating across multiple Verification Methodologies and tools:
- Simulators & EDA tools (e.g., Synopsys/Fairway, Mentor Questa)
- Coverage Drives Synthesis (Track Coverage of functional scenarios).
- Gate-Level Simulation and Waveform Viewers (for debugging).
- Formal Proof Tools (Model Checking Tools) for automated verification.
Independence & Ownership
- Ability to independently execute your task from conception through execution.
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