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CPU Research Engineer

Cambridge
Posted about 21 hours ago
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CPU Research Engineer – Contract

Location: Cambridge, UK
Working arrangement: Onsite
Employment type: Contractor

We are supporting a leading technology organisation in Cambridge that is looking for an experienced CPU Research Engineer to join a highly specialised processor architecture team.

The position will focus on researching and evaluating new CPU microarchitectural techniques, with particular emphasis on out-of-order execution, instruction-level parallelism and performance-per-watt optimisation for mobile processors.

Responsibilities

  • Research and develop new out-of-order execution techniques to improve CPU IPC and energy efficiency.
  • Analyse and optimise CPU frontend pipeline stages, including branch prediction, instruction fetch and decode.
  • Investigate performance bottlenecks across the out-of-order backend, including issue queues, register renaming, reorder buffers and execution units.
  • Develop, extend and maintain cycle-accurate microarchitectural simulation models.
  • Evaluate CPU design trade-offs using tools such as gem5, Sniper, ChampSim or similar internal simulation platforms.
  • Propose practical microarchitectural enhancements targeting performance-per-watt improvements.
  • Conduct workload characterisation and microarchitectural profiling using simulation data and hardware performance counters.
  • Analyse mobile and compute-intensive workloads to identify architectural limitations and optimisation opportunities.
  • Review state-of-the-art academic research and translate relevant concepts into practical CPU design proposals.
  • Collaborate with CPU architects, compiler engineers, performance engineers and other research teams.

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£35,000/yr

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Required Experience

  • Master’s degree or PhD in Computer Science, Computer Engineering, Electrical Engineering, Physics or a related technical field.
  • Strong knowledge of advanced computer architecture, superscalar processors and out-of-order execution.
  • Deep understanding of speculative execution, branch prediction and instruction-level parallelism.
  • Experience with cycle-accurate microarchitecture simulation and performance modelling.
  • Strong programming skills in C, C++ and Python.
  • Experience with Arm64, AArch64 or RISC-V assembly language.
  • Understanding of compiler principles, including instruction scheduling, register allocation and code generation.
  • Experience conducting workload profiling, benchmark analysis or performance-counter-based investigations.
  • Ability to independently research complex technical topics and translate findings into implementable architectural proposals.

Desirable Experience

  • Experience developing or modifying gem5, Sniper, ChampSim or similar detailed CPU simulators.
  • Knowledge of advanced branch predictors, instruction prefetchers and data prefetching mechanisms.
  • Experience with LLVM or GCC backend development.
  • Knowledge of profile-guided optimisation and feedback-directed optimisation.
  • Experience implementing custom ISA extensions or compiler support for new architectural features.
  • Experience with operating-system kernel development, scheduling or memory-management internals.
  • Knowledge of binary translation, dynamic binary instrumentation or JIT compilation.
  • Familiarity with Arm security technologies such as CFI, PAC, BTI or MTE.
  • Experience integrating ISA simulators with compiler or software toolchains.
  • Knowledge of processing-in-memory, near-data processing or chiplet-based architectures.
  • Understanding of domain-specific processors and accelerator-compiler co-design.

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Candidate Profile

The successful candidate will be highly independent, research-driven and comfortable working on complex, open-ended CPU architecture problems.

This opportunity would particularly suit someone with experience in CPU microarchitecture research, processor performance modelling, out-of-order core development or advanced computer architecture simulation.

The role is based onsite in Cambridge and is offered on a contract basis.

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Skills

CPU Microarchitecture
Out-Of-Order Execution
Instruction-Level Parallelism
Performance Modelling
C
C++
Python
Arm64
AArch64
RISC-V
Cycle-Accurate Simulation
Branch Prediction
Workload Profiling
Benchmark Analysis
Compiler Principles
Performance Counters

Location

Cambridge, England, United Kingdom

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