IC Resources
Design Verification Engineer

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The Role
This is a fantastic opportunity to join a well-established semiconductor company as they continue to grow their multi-disciplinary Verification team. The group has ambitious expansion plans and is seeking Design Verification Engineers to work on complex technical challenges, delivering innovative end-user solutions for leading global consumer brands.
As a Design Verification Engineer, you will be involved in all aspects of digital verification for complete mixed-signal IC developments. You will work on sophisticated verification environments and actively contribute to the ongoing improvement of verification methodologies.
This is an excellent opportunity to become deeply involved in cutting-edge projects within a global organisation. In return, the company offers a strong benefits package, including personal and professional development, a uniquely flat culture, and a competitive compensation package including RSUs.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Responsibilities
The team is hiring across multiple levels, from Mid-Level through to Staff. More senior engineers will have opportunities to take on additional responsibilities, such as:
- Supporting and mentoring junior engineers
- Driving improvements in verification methodologies
- Leading verification activities for larger or more complex projects
Required Skills & Experience
- Metric-driven verification, including:
- Verification planning
- Requirements extraction
- Directed and constrained-random verification
- Functional and code coverage analysis
- Strong SystemVerilog, including SVA (SystemVerilog Assertions)
- Testbench development using verification frameworks (e.g. UVM)
- Strong debugging skills
- Scripting experience with TCL or Perl
- Power-aware verification using CPF/UPF
- Formal verification and verification qualification techniques (nice to have)


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Location
- Edinburgh (Newbury can be considered)
Working Model
- Hybrid (2+ days per week in the office)
Relocation & Visa Sponsorship
- Available if required
For more information, please contact Rachel Mason at IC Resources.
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