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Raspberry Pi DFT Engineer Opportunity
Raspberry Pi is seeking a DFT engineer to join our expanding ASIC team to help deliver our next-generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second-generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.
As a DFT Engineer you will be responsible for creating, implementing, and verifying DFT solutions on future Raspberry Pi ASIC designs to ensure quality standards are maintained for products shipping in volume. You will use advanced DFT methods to balance requirements for test coverage, cost, and time to market.
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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
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Key Responsibilities
- Define a suitable DFT strategy at chip, subsystem, and IP level, including structural and functional methods, and make pragmatic trade-offs between methods.
- Experienced with Tessent DFT tool flow for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL, in both flat and hierarchical designs.
- Experienced in verification of DFT structures, and debugging related issues.
- Support DFT through implementation and sign-off, including generating timing constraints and debugging timing, power, and formal equivalence issues.
- Willing to share knowledge and mentor other members of the team.
Requirements
Key requirements:
- Experience with IC development flows.
- Experience with Tessent DFT tools.
- A good level of understanding of complex IP issues for DFT, including on-chip clocking.
- Experience in ATPG, MBIST, and simulation debug, including UPF-related issues.
- Willingness to contribute and share activities with a wider team.
- Good scripting skills, including TCL.


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The following would also be useful:
- Ability to demonstrate an understanding of advanced silicon technologies and fault models.
- Familiarity with test access standards, e.g. IJTAG/IEEE1687.
- Familiarity with vector translation and bring-up on ATE platforms.
In addition, candidates should have:
- A degree in electronic engineering, computer science, or a related discipline.
- A proactive approach to troubleshooting.
- The ability to coach other members of the team.
Benefits
- Competitive salary based on level of experience.
- Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme.
- Life assurance of 4 × base salary.
- Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long-term illness or absence from work.
- Private medical insurance (medical history disregarded).
- Access to our electric vehicle salary sacrifice scheme, subject to eligibility.
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