
How your CV stacks up
Upload your CV to see how well it fits this job role
?%
Help Build the Next Generation of AI Silicon
I'm currently working with an exciting, well-funded semiconductor company developing next-generation AI hardware designed to overcome one of the biggest challenges facing modern computing.
As AI workloads continue to increase in complexity, the demand for faster, more efficient silicon has never been greater. This team is developing a cutting-edge AI accelerator architecture that will help redefine the future of high-performance computing.
They're now looking for a DFT Engineer to join the team implementing Design-for-Test for a large, multi-core AI accelerator ASIC.
You'll play a key role in delivering a scalable, production-ready DFT solution, working across scan implementation, ATPG, memory test and silicon bring-up. This is an excellent opportunity to develop your expertise while working alongside experienced engineers across architecture, RTL, physical design and product engineering.
Responsibilities
- Contribute to the DFT architecture of a complex multi-core AI accelerator SoC
- Integrate DFT methodologies and tools into the overall ASIC design flow
- Implement scan insertion, scan compression and associated test logic
- Generate, analyse and debug ATPG patterns for structural fault coverage
- Support MBIST implementation for large embedded memory arrays
- Work closely with Physical Design teams to ensure robust scan chain implementation and timing closure
- Develop scripting and automation to improve DFT efficiency and workflows
- Support silicon bring-up, manufacturing test and post-silicon debug
- Collaborate with Product and Test Engineering teams to support ATE bring-up, production test and yield improvement
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
Start with a chat, not a search bar
Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
See breakdownIt searches the market for you
Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
What they're looking for
- Degree in Electronic Engineering, Computer Engineering or a related discipline
- Experience in DFT, digital IC design or ASIC development
- Good understanding of:
- Scan architecture
- ATPG
- MBIST
- Digital test methodologies
- Familiarity with industry-standard EDA tools
- Scripting experience using Python, Tcl or similar languages


Get help with your application
Your very own career expert that helps elevate your application to the next level.
You'll enjoy solving technical challenges, working collaboratively across engineering disciplines and developing your expertise on complex, leading-edge silicon.
You're naturally detail-oriented, enjoy working on large-scale ASICs and are keen to grow your knowledge of Design-for-Test within a high-performing engineering team.
Why Join?
- Work on genuinely innovative AI silicon with real-world impact
- Be part of a highly collaborative engineering culture
- Gain exposure across the full ASIC development lifecycle, from architecture through to silicon bring-up
- Work alongside experienced experts across hardware, software and systems engineering
- Take ownership of meaningful technical challenges while continuing to develop your career
If you'd like to hear more, I'd be happy to share further details in confidence. For more information, contact Rachel at IC Resources
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
Skills
Location