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MRL Consulting Group | Global Niche Technology Recruitment

Digital Design Engineer - Power Management

Cambridge
Posted about 23 hours ago
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Job Title: Digital Design Engineer

Scope

We are seeking a Digital Design Engineer to join our dynamic and innovative team working in the growing markets of mixed-signal chips with signal processing IPs, ARM processors, and AMBA bus interfaces. Our products include wireless chargers, PMICs, and more, serving applications in mobile devices, tablets, data centers, and automotive markets.

As part of the Digital Design Team, you will play a key role in creating efficient digital designs for cutting-edge mixed-signal applications.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Key Responsibilities

  • Participate in all aspects of digital controller, interface, and algorithm development.
  • Perform RTL design of digital circuits for mixed-signal applications.
  • Engage in all stages of product development: specification, design, synthesis, verification, timing analysis, design-for-test, backend verification, and silicon debug.
  • Conduct simulation and verification in both digital and mixed-signal environments.

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Requirements

  • Experience: 5–8 years in digital circuit design
  • Proficiency in Verilog RTL design and test bench creation (preferably self-checking).
  • Excellent debugging skills for efficient bug diagnosis and closure.
  • Knowledge of low-power design concepts and clock domain crossing issues.
  • Familiarity with Cadence design tools.
  • Basic understanding of analog IC technologies
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Skills

Digital Circuit Design
Verilog RTL Design
Test Bench Creation
Debugging Skills
Low-Power Design
Clock Domain Crossing
Cadence Design Tools
Analog IC Technologies

Location

Cambridge, England, United Kingdom

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