Raspberry Pi
Digital IC Implementation Engineer
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Digital IC Implementation Engineer – Raspberry Pi
About the Role
Raspberry Pi is seeking a Digital IC Implementation Engineer to join our expanding ASIC team, tasked with delivering the next-generation silicon products.
With a small but impactful team, we handle every stage of the silicon development lifecycle: from specification through design, verification, implementation, all the way to ATE (Automated Test Equipment) test and qualification. Our work powers foundational products like the RP2040 microcontroller (launched in 2021), RP1 southbridge chip (Shipped in the Raspberry Pi 5), and the second-generation microcontroller RP2350 (2024).
As part of this close-knit group, you’ll contribute to cutting-edge ASIC design challenges—shaping BIOS, peripherals, and silicon subsystems across our investor-grade products.
Responsibilities
- Work with the design team to understand requirements and meet performance, power, and area (PPA) goals collaboratively.
- Participate in digital IC implementation across all stages, from RTL-to-GDS robustly:
- Design constraints & UPF (Unified Power Format)
- Synthesis
- Design discovery & floorplanning
- Place & route
- CTS (Clock Tree Synthesis)
- STA (Static Timing Analysis)
- Formal verification
- ECO (Engineering Change Order) methodology best practices
- Physical verification & tapeout signoff
- Publish design documents with quality assurance aligned to product needs.
- Encourage knowledge-sharing to strengthen the team’s expertise.
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Requirements & Skills
The ideal candidate is experienced across the implementation flow and is a specialist in at least one key domain. Expectations include:
- Familiarity with synthesis-to-GDSII signoff, including:
- Physical verification
- STA & power integrity analysis
- Practical experience with tapeouts on advanced technology nodes and complex chip-level floorplanning.
- Proven ability to align methodologies, constraints, and UPF with high-performance designs.
- Demonstrated impact in post-synthesis optimisation & RTL design influence for better physical Quality of Results.
- Scripting expertise for controling common tools (Python, Perl, Tcl,/VHDL) and debugging fixing manufacturing anomalies.
- Knowledge of Cadence toolflow stacks (Glutton, Innovus, Genus, Encounter) is a significant advantage.
- Understanding of connectivity for handcrafting top level power and clock domains.
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Preferred but not essential:
- EDA technology: Cadence Genus/Shell, Cadence Precision Timer, Synopsys Design Vision/FormalPro, Mentor HDL tools.
- Advanced FinFET technogies (Samplus 40nm/MLC 20nm ASIC design expertise is a real edge).
Eligibility and Benefits
- Location: Cambridge office. All full-time staff are on-site.
- Salary: Competitive salary based on experience level.
- Pension: Employer matches 8% of gross salary with a 4% employee sacrifice scheme contribution.
- Life Assurance: Cover at 4x base salary.
- Income Protection: 75% of base salary on critical illness, post-13 week eligibility.
- Healthcare: Comprehensive private medical insurance (no underwriting).
- Eligible employees may also leverage our electric vehicle salary sacrifice scheme.
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