Graphcore
Director, Silicon Logical Design
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Director, Silicon Logical Design
Director of Silicon Logical Design – Graphcore
About Graphcore
At Graphcore, we’re building the future of AI compute.
We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack – from silicon and software to datacenter-scale infrastructure.
As part of the SoftBank Group and backed by substantial long-term investment, we are delivering core technology into the fast-growing SoftBank AI ecosystem.
We are expanding our teams globally to meet the vast opportunities in artificial intelligence, combining the brightest minds to tackle the toughest challenges while offering everyone the chance to impact the company, its products, and the future of AI.
Job Summary
We are seeking an experienced Director of Silicon Logical Design to lead and scale our Logical Design group within the Silicon department. This role will ensure alignment with Graphcore’s silicon and product strategy by defining the technical direction, execution quality, and team development for microarchitecture and RTL design.
The Director will oversee high-performance, power-efficient silicon delivery through close collaboration with Architecture, Physical Design, Verification, DFT, and Program Management teams.
The Team
The Logical Design team designs and delivers the microarchitecture and RTL—the foundational blocks that realise our advanced chip architectures. As Director, you will:
- Steer this multi-site team to its full potential
- Strengthen cross-functional partnerships
- Drive advances in our design flows and capabilities
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Responsibilities and Duties
Leadership & Strategy
- Define and execute a strategic roadmap for Logical Design, ensuring alignment with Graphcore’s silicon and product roadmap
- Lead, grow, and mentor a high-performance RTL/micro-architecture design organisation
- Establish world-class design methodologies, documentation standards, and quality metrics
- Drive continuous improvement in team structure, workflows, tooling, and design processes
Technical Ownership
- Provide technical oversight of microarchitecture and RTL development for major blocks and subsystems
- Guide architectural feasibility studies and micro-architecture trade-offs
- Oversee the integration of third-party IP, custom design blocks, and high-performance application-specific subsystems
- Ensure rigorous design sign-off via linting, synthesis, CDC/RDC, timing closure, and full coverage reporting
Cross-Functional Collaboration
- Collaborate closely with Physical Design, Verification, DFT, Architecture, and Program Management for cohesive planning and execution
- Lead cross-team communication across global sites, promoting alignment on priorities and deliverables
- Support silicon bring-up and debug efforts with deep expertise in RTL behaviour and architecture
Execution and Delivery
- Own delivery of high-quality, on-schedule RTL for multiple concurrent silicon programs
- Implement scalable project planning and risk management
- Advocate for design automation and infrastructure improvements to boost productivity and design quality
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Essential Skills and Experience
- Degree in Computer Science, Electrical Engineering, or a related discipline (advanced degree preferred)
- Extensive experience in digital logical design, microarchitecture, and RTL for large-scale, high-performance semiconductor projects
- Proven track record of leading and developing technical teams within the semiconductor industry
- Deep expertise in SystemVerilog or VHDL with a practical understanding of modern digital design flows
- Strong ability to diagnose and resolve complex design challenges, including scripting/programming (Python, Tcl, etc.)
- Demonstrated excellence in cross-functional global leadership and communication with technical teams
- Strong organisation and prioritisation skills for success in fast-paced environments
Desirable Experience
- Experience in processor or accelerator microarchitecture
- Working with high-speed serial interfaces and complex, high-bandwidth IP blocks
- Expertise in arithmetic pipeline design and floating-point datapath optimisation
- Proficiency in advanced synthesis, timing analysis, power modelling, and logical equivalence checking
- Experience in design-for-test methodologies
- Comprehension of power integrity and silicon-level device considerations
- Background in silicon bring-up and post-silicon validation
- Expertise in multiproject execution and program planning for semiconductor delivery
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