Apple
Early Career - PMU Design Verification Engineer
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At Apple, we work every single day to craft products that enrich people's lives.
Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and outstandingly talented Design Verification Engineer. As a member of our dynamic group, you will have the unique and exciting opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day!
Apple’s PMU Hardware Tech team are responsible for delivering the power in a highly configurable and controlled way to the high end Apple SoCs, which power everything from Apple Watch, AirPods, and Apple TV to iPhone, iPad, Mac and Vision Pro. We are looking for a recent Graduate or Junior Digital Design Engineer, with the talent, ambition and passion, to innovate the way we verify our next generation of power management silicon, to provide industry leading power efficiency, achieve customer expectations of device performance, battery efficiency, and welcome you to work among the industry’s best.
We are looking for a Design Verification Engineer who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
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DESCRIPTION
In this role you will develop verification plans in coordination with design leads and architects. You'll be responsible for planning, building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure an efficient verification flow.
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MINIMUM QUALIFICATIONS
- BSc/MSc/BEng/MEng/PhD in Electronic Engineering or an equivalent field
- Good understanding of System Verilog
- Basic understanding/experience of verification methodologies such as UVM
- Understanding of digital logic circuits
- Experience with digital logic simulation
- Experience with Python, Perl or TCL
- Ability to work well in a team and be productive under tight schedules
- Strong communications skills, self-motivated and well-organised, combined with ability to collaborate
- Strong analytical/problem solving skills
- Fluency in English language (written and verbal) is required
PREFERRED QUALIFICATIONS
- Understanding of Analog or mixed signal circuits is desirable but not required
- Knowledge of constrained random verification is desirable but not required
- Some international travel may be required.
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