Raspberry Pi
Experienced IC Design Engineer

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Senior ASIC Design Engineer
Role: Experience IC Design Engineer
Raspberry Pi is seeking an experienced IC Design Engineer to join our expanding ASIC team, where you will help deliver next-generation products. We’ve built our own silicon, releasing the RP2040 microcontroller in 2021, the RP1 southbridge chip for Raspberry Pi 5, and more recently, the second-generation microcontroller, RP2350, in 2024.
About the Team & Role
Our ASIC team is responsible for the entire silicon flow—from specification to design, verification, and implementation—including ATE test and qualification. With a small, agile team, you’ll be involved in all critical steps of bringing products to market.
As the Senior ASIC Design Engineer, you will:
- Take ownership of front-end tasks, including specification, design, verification, and implementation.
- Collaborate with specialists across teams while working both autonomously and in dynamic cross-functional environments.
- Specify and configuring IP and systems, ensuring seamless integration.
- Work closely with the software team to bridge hardware-software gaps.
- Support FPGA platforms for early development and verification.
- Troubleshoot and resolve power and timing-related issues with the implementation team.
- Drive engineering trade-offs while balancing cost, schedule, and PPA (Power, Performance, Area) metrics.
Core Responsibilities
- Design, IP integration, and verification planning/execution
- Specify and configure IP and systems with architectural oversight
- Collaborate with the software team (real-time OS, drivers, and applications)
- Utilise FPGA platforms for fast prototyping and verification
- Support the implementation team on power efficiency and timing closure
- Document findings and decisions clearly for engineers and stakeholders
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
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Key Requirements
- 10+ years of experience in SoC or MCU architecture, with hands-on ownership of chip or non-trivial subsystem in at least one tape-out
- Deep expertise in modern microcontroller/processor design, including:
- Real-time behaviour & deterministic interrupt handling
- Low-power modes & optimisation (e.g., sleep/wakeup states)
- Flash/SRAM hierarchies & cache utilisation
- Common peripherals (e.g., SPI, I²C, UART, USB, PIO-style fabrics, ADC/DAC, timers)
- Strong understanding of SoC integration concepts such as:
- Coherent & non-coherent interconnects (e.g., AXI, AHB, APB)
- Cache hierarchies and memory controllers
- DMA, security architectures (e.g., TrustZone), and multi-domain operation (OS + real-time)
- Implementation proficiency across:
- RTL coding (SystemVerilog), verification methodology (UVM, formal, emulation/FPGA)
- DFT (Design for Test), timing closure, power analysis, and physical design constraints
- Track record of making clear trade-offs under pressure, communicating them effectively across disciplines
- Practical experience with embedded software (C for microcontrollers), understanding SDK/toolchain implications
- Ability to articulate complex architectural ideas to both technical and non-technical stakeholders
- Reliable self-management, strong schedule adherence, and proactive problem-solving


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Bonus Skills:
- Experience with Cadence simulation tool flow
- Hands-on with ASIC/FPGA synthesis, implementation, DFT, and debugging
- Familiarity with test vectors, burn-in, and post-silicon bring-up
Good to Have
- Scripting fluency (Bash, Python, Tcl, etc.) for automation
- Knowledge of industrial electronic manufacturing (ATE)
Location & Compensation
Location: Cambridge, UK (with full-time office attendance). Competitive salary aligned with experience level. Benefits include:
- Pension contributions (8% employer match) when you contribute 4%
- Life assurance (4× base salary)
- Income protection (75% of base salary following 13 weeks’ absence)
- Private medical insurance (underwritten without reference to medical history)
- Access to an electric vehicle salary sacrifice scheme (subject to eligibility)
Why Join Us?
- Be part of the next-generation products at Raspberry Pi, including RP2350 and beyond
- Work on full-stack silicon development, shaping real-time and OS-class subsystems
- Collaborate with a small yet highly skilled ASIC team at a vibrant company
- Join a team with a shared drive for high-quality, real-world engineering at scale
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
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