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Elite People Partners Ltd

Formal Verification Engineer

Oxfordshire
£50k – £130k/yr
Posted 2 days ago
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Formal Verification Engineer

Formal Verification Engineers £50k–£130k | Oxford


About the Role

Our semiconductor client is seeking Formal Verification Engineers to join their cutting-edge SoC team for ASIC development. The ideal candidate will collaborate with multidisciplinary experts to contribute to industry-leading projects.


Key Opportunities

  • Tailored training to deepen technical expertise and advance career growth
  • Exposure to RTL Design, Formal Verification, and DevOps
  • Direct mentorship from a highly accomplished Senior Director and team
  • Multidisciplinary teamwork tackling complex design and verification challenges
  • Engagement in high-volume data centre and enterprise products used by industry leaders

Eligibility & Experience

We are looking for engineers with 5–15+ years of experience in:

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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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  • Essential Qualifications & Skills

    • 10+ years of digital ASIC design and verification experience
    • Formal Verification expertise (e.g., Jasper Gold, VC_Formal)
    • Ability to:
      • Translate design requirements → RTL
      • Define functional verification requirements
      • Develop SystemVerilog UVM test benches
      • Work with scripting languages (e.g., Perl, Python, TCL) and REST APIs
    • Strong collaboration, communication, and team-playing skills
  • Desirable Skills

    • SV UVM 1800.2 experience
    • Fluency in C/C++
    • Familiarity with storage interfaces: SAS, PCIe, NVMe (preferred), or SATA

Compensation & Benefits

  • Salary: £50k–£130k (depending on role and experience level)
  • Performance Bonus: 10–20%
  • Annual Leave: 25 days + 8 bank holidays
  • Hybrid Work: 3 on-site days per week
  • Pension: 8% match via employer contributions
  • Comprehensive Benefits:
    • Life assurance
    • Income protection
    • Private medical cover
    • Employee Supported Volunteering
    • Employee Assistance Programme (wellbeing, financial/legal support)
  • Career Growth: Training and development opportunities
  • Relocation/Visas: Sponsorship and support offered as needed

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Recruitment Process

  1. Video Call (Stage 1)
  2. Video Call (Stage 2)
  3. On-site Interview (team meetup and tour) Total timeline: 2–3 weeks (flexible based on availability)
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Skills

Formal Verification
ASIC Design
Verification
RTL Design
Systemverilog
UVM
Scripting Languages
REST APIs
Team Player
Communication Skills
EDA Tools
Data Centre Products
International Collaboration
C/C++
Storage Interfaces
NVMe

Location

Oxfordshire, England, United Kingdom

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