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DEEPX

[HW] Entry-level Engineering (Bachelor’s/Master’s/PhD/전문연구요원)

Stoke-on-Trent
Posted about 15 hours ago
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Frontier of On-device AI Semiconductors

for Everyone, Everywhere

About DeepX Co., Ltd.

DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.

By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.

Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.

We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link

★ If you want to be part of world-class innovation? Please talk with us.

★Explore our journey: The DEEPX White Paper ☞ Link

You may apply for any position in the Hardware Engineering.

RTL Design (Hardware IP)

  • Design RTL-based hardware IPs related to AI processor architecture and development

Design Verification

  • Digital Circuit Design & Verification: Develop testbenches and perform simulations using System Verilog/UVM
  • Verification Planning & Execution: Build verification environments and analyze functional coverage
  • RTL Design Review & Debugging: Analyze and fix design issues
  • Collaboration & Documentation: Document design specifications and verification results

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

P

Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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It searches the market for you

Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.

Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

Only hits

No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.

FPGA

  • Build FPGA platforms and develop prototypes related to AI processor architecture and development

SoC ASIC Design

  • Design SoC ASICs focused on AI processor architecture and development

PCIE Link (Controller) Design

  • Design and implementation of PCIe Controller and Link Layer logic for NPU SoCs
  • Integration and verification of PCIe IP in RTL design
  • Development of PCIe protocol logic including configuration, flow control, and error handling
  • Performance optimization and validation of PCIe interfaces
  • Collaboration with verification, firmware, and system teams for end-to-end PCIe functionality

NPU Architect

  • Explore, share, discuss, and finalize NPU architectures that meet specification requirements
  • Collaborate to develop profiling tools tailored to internal and customer needs
  • Predict hardware-efficient performance quickly and accurately for AI networks (C++, SystemC)
  • Work with deep learning, RTL, and compiler teams to design optimized NPU architectures and engineering methods
  • Propose advanced NPU structures considering new network characteristics and system components

DDR Memory Subsystem

  • 3rd-Party DDR IP Integration and SoC Interface Verification
  • Pre-Silicon Verification
  • Firmware Integration and DDR Initialization/Training
  • Post-Silicon Validation & System Bring-up
  • Mass Production Test and Yield Analysis

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System HW

  • Review PCB layouts and designs based on customer specifications
  • PCB design considering Signal & Power Integrity, thermal management, etc.
  • FPGA board design and inter-board design
  • ARM-based System SoC EVK & RDK board design and testing
  • Manage PCB/SMT manufacturing vendors
  • Source new components
  • Provide hardware support to customers

Recruitment Process

  • Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion

※ The recruitment process may vary depending on the position and application content.

※ Candidates with less than 3 years of experience are required to submit their academic transcripts.

Employment Type

  • Full-time (3-month probationary period with 100% compensation)

Working Hours

  • Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)

Notes

  • If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
  • A 3-month probationary period applies after joining, with no reduction in salary or benefits.

Benefits

  • 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
  • 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
  • 점심식사 + 아침 & 저녁식사 지원
  • 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
  • 사우나가 포함된 피트니스 비용 지원
  • 연 1회 종합건강검진 지원 (배우자 포함)
  • 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
  • 설/추석 명절 상여금 지급
  • 축하와 위로를 위한 경조휴가 및 경조금 지원
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Skills

RTL Design
Digital Circuit Design
Verification Planning
FPGA Development
SoC ASIC Design
PCIe Controller Design
NPU Architecture
DDR Memory Subsystem
PCB Design
System Design
C++
SystemC
Simulation
Documentation
Collaboration
Debugging

Location

Stoke-on-Trent, England, United Kingdom

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