Raspberry Pi
IC Verification Engineer

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About the Role
Raspberry Pi is seeking an IC Verification Engineer to join our expanding ASIC team to help deliver our next-generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second-generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.
As a Verification Engineer, you will take ownership for IP and chip level verification planning and execution, and will be constantly interacting with the design team, composing detailed verification plans and creating test benches from scratch or using shared verification components.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
The Successful Candidate
- A self-starter, able to identify, plan, and execute a wide range of verification tasks as required.
- Able to demonstrate a good understanding in all aspects of the design flow from synthesis through to silicon sign-off.
- Able to analyse and debug non-trivial test failures.
- Able to demonstrate excellent interpersonal and communication skills.
Requirements
Key Requirements
- Hands-on experience with at least three projects.
- Experience of creating test benches from scratch, using Systemverilog, Python, or UVM.
- Experience of writing embedded C, ideally for Cortex M-class MCUs.
- Good technical understanding in at least one complex IP protocol, e.g. PCIe, HDMI, USB, SDIO, AMBA bus architectures.
- Ability to write functional coverage and SVA.
- Good understanding of design/front-end processes.
- Experience with low-power simulations.


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Additional Skills
- SoC verification concepts: memory caches, DMA, security architecture (TrustZone or equivalent).
- Formal experience with Jasper or similar tools.
- Experience of Cadence simulation tool flow including gate-level simulation.
- Scripting languages: Bash, TCL, Make, YAML, etc.
Location
The role is based in Cambridge with an expectation of full-time office attendance.
Benefits
- Competitive salary based on level of experience.
- Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme.
- Life assurance of 4 × base salary.
- Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long-term illness or absence from work.
- Private medical insurance (medical history disregarded).
- Access to our electric vehicle salary sacrifice scheme, subject to eligibility.
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