SiFive
Interconnect Design Engineer
How your CV stacks up
Upload your CV to see how well it fits this job role
?%
Interconnect Design Engineer
---
# **About SiFive**
SiFive are the pioneers who introduced **RISC-V** to the world. We’re transforming the future of compute by unleashing the potential of RISC-V in the world’s leading performance and most data-intensive applications. Our unrivalled **compute platforms** empower global technology innovators—across artificial intelligence, machine learning, automotive, data centers, mobile, and consumer—to deliver cutting-edge solutions.
Together, we build processors with a mission: **to make the world a better place, one processor at a time**. Join us if you’re driven by innovation and want to create groundbreaking technology.
Explore our [website](link) and [Glassdoor](link) to learn how we’ve (**four-time**) won the GSA’s *Most Respected Private Company Award*.
---
## **The Role: Hardware Engineer (Staff Level)**
SiFive seeks a **hardware engineer** passionate about designing industry-leading **CPU and interconnect IP** to accelerate adoption of **RISC-V** across diverse industries. We leverage software agility to drive scalable hardware design, building configurable IP using **Chisel/Scala** for mass-market relevance.
### **Your Challenge**
- Architect the **best interconnect IP in the world**, built on **RISC-V and TileLink**
- Master **RTL generators** for hardware—utilizing domain-specific languages to evolve circuits dynamically
- Innovate in a high-speed collaborative environment, balancing speed, quality, and performance
---
## **Responsibilities**
- **Lead IP Development**:
- Design enhanced **TileLink**, cache controllers, protocol bridges, and uncore logic as **RTL generators** in **Chisel**
- Architect **fully-configurable** generators, ensuring seamless, efficient interconnections
- Optimize **multi-core and multi-system coherence** for superior performance
- **Engineering & Verification**:
- Contribute to SiFive’s **Chisel/FIRRTL** framework, expanding documentation, testbenches, and software
- Develop **sandbox verification** and collaborate with verification teams to execute **throrough test plans**
- **Collaboration & Documentation**:
- Share knowledge through ** améning documentation** and emphasizing **team engineering**
---
## **What We Look For**
### **Must-Have Knowledge & Experience**
- Deep expertise in **cache/mecache coherency** architectures
- Familiarity with **NoC/interconnect fabrics**
- Hands-on experience with **industry protocols** (AXI, AHB, APB, CHI)
- **Software-first** mindset:
- Object-oriented, aspect-oriented, and functional programming
- **Templated metaprogramming** (any language)
- Compiler infra (especially for **domain-specific languages**) and **intermediate representations**
- **Test-driven devotion** with adaptive unit-test experience
- Proficiency in **verilog/System Verilog/VHDL** for hardware design
- BS/MS in **EE, CE, CS**, or equivalent industry experience
Reasons to use Rodeo
Start with a chat, not a search bar
Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
It searches the market for you
Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Nice-to-Have
- Chisel/Scala/Bluespec expertise
- Exposure to RISC-V specifications
- Experience with Git/GitHub, Jira, Confluence
Pay & Benefits
SiFive aligns compensation with market and location benchmarks, adjusted based on role-specific qualifications/time in role. Base rates for this Staff position reflect competitive equity.
Compensation Range (U.S-Based)
- Base: $178,848.00 - $218,592.00
- Additional incentives (variable compensation, equity)
- Comprehensive benefits package: healthcare, retirement, paid time off (PTO), etc.
Additional Information
- Background Check: Successful pre-hire verification required
- Export Control: Must validate eligibility for access to U.S. export-regulated tech
- Inclusivity: SiFive is an equal opportunity employer (E-Verify company), championing diversity and collaboration
#TheFutureStartsWithRISC-V
``` => (Remove the first markdown block, do not wrap output in anything.)
Here's the correctly formatted Markdown output:
Staff Hardware Engineer
(Chip Design & Interconnects)
About SiFive
We pioneered RISC-V—technology that unlocks powerful, open compute for industries like AI, automotive, and data centers. Our customizable IP platforms and hardware software engineering approach accelerate market impact through domain-specific languages.
Why join? Parce que nous innovons with purpose—creating hardware that refugees barriers and enhances lives. Join a team honouré telah memenangkan GSA’s Most Respected Private Company Award for the fourth consecutive year.
Preply pour explorer notre mission : SiFive Career Page
The Role
SiFive seeks a hardware engineer to contribute to our ground-breaking CPU and interconnects for RISC-V. Pasang-garis target spotlight on redefining TileLink and caching architectural frontiers.
Lights conté
- Transform open RISC-V standards into high-performance interconnect architecture
- Maintenances firmware project pipelines using Chisel DSL technologies
- Engages with industry benchmarks to define new hardware efficacy metrics
- Outputs scalability-focused, prioritizing modularity and optimizer/synthesizer interop
Get help with your application
Your very own career expert that helps elevate your application to the next level.
Missions Clés
Design & Deployment Responsibilities:
- Design and implement RTL generator for Tilelink interconnect, memory controllers, cache coherence
- TierRUN configurability leveraging reflective properties for scalable design systems
- Magic mapping and interop bridging across protocol boundaries (TLV, AXI, AVS)
- Exploiting SIL method@ddd Unicode configuration tools that harmonise development workflows.
Collaboration & Execution:
- Collaborate with verification teams; direct unit testing for RTL generator correctness
- Create/sustaining high-quality documentation and tools contribution educate internal & external stakeholders.
- Participer à agilee meetings; share new ideas intérieure confident teams
Open Innovation Integration:
- Contribute to Scala/Chisel/FIRRTL framework flows, comprising programmable suites and visualization
- Drive virtuo-portfolio testbench stories–python/Jupyter ecosystem befindet result-rounding specs
Crew Qualifications
Résشاء Essentielle
- Backend Architecture Foundations:
- Triangle-devstarty network stuff on/Cool cache coherence (MESI/CMA/XMf)
- Score experience with Network-on-Chip (NoC) configurations
- Design with modularity:
- Tetrameters elaborator nach-member problem solving geoganglial commands
- Software Parity Mindset:
- Deep exploration domain-specific interpreted/mini-languages with compilers (for hardware too!)
- Type systems, functional paradigms, unitized metaprogramming
- RTL roles: Trivalbus expertiseigen grafiken with staats
École recommandable
- RISC-V inclination (2nd-level preferred; SW asset)
- Scala/Chisel/SBT syntax (implicit commitment to software-native hardware)
- GitHub communning convention, tooles
Compensation Échelle
| Compensation Package Components | Range (Status-Based Deciled) |
|---|---|
| Base Salary (US Allocations) | $178,848–$218,592 |
| Incentive Variable Pay | Subject; aligns to location + tenure affordability |
| Equity | Supra company contributės? |
Politiques:
- Evaluation: US veto stateud-asymmetrical reference vérification
- Divinity Requirements: Participating procédure gala employment vaccinated to affirmative action
SiFive Is Anyscale Talent Catalyzer Generate applicant sous commitment fulfilment! #Computenam Stein BRC - Not Limited
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
Skills