SiFive
Interconnect Design Engineer
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Staff Hardware Engineer
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest-performance and most data-intensive applications. SiFive’s unrivaled compute platforms enable leading technology companies worldwide to innovate, optimize, and deliver advanced solutions across chip design markets:
- Artificial intelligence
- Machine learning
- Automotive
- Data center
- Mobile
- Consumer
With SiFive, the future of RISC-V has no limits.
At SiFive, we connect with passionate, talented individuals dedicated to driving innovation and shaping the world. Our success stems from a culture of collaboration and collaboration across diverse, groundbreaking teams—catalysts for Society-changing impact, answered processor at a time
Ready to be part of it?
Discover SiFive’s triumphs—[four-time U.S. Most Respected Private Company honoree by the GSA]—and why our Glassdoor pages are beacons for both ambition and الكشف on award-winning transparency: [Visit SiFive | Glassdoor]
The Role
SiFive is seeking a staff-level hardware engineer—mastermind behind industry-leading CPU and interconnect IP, championing the RISC-V revolution. Your role: architect massively configurable IP to revolutionize SoC designs, accelerate time-to-market, and unleash RISC-V’s potential across industries.
Here’s the gameplan:
- Design as code: Adapt an agile software-engineering mindset to hardware development, crafting RTL generators in Chisel with support for Scala.
- (lineable power: Enhance every CPU disipline – TileLink interconnects, cache controllers, protocol bridges, and a uncore logic, ensuring visions become real RISC-V assets.
- Cross-platform cohes sorce: Solve efficiency/performance tradeoffs continually facing multi-core/multi-system systems, where latency and throughput.
- Scalability on demand: Eliminate “spaghetti connections” with algorithm-driven, self-optimizing configurations.
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Mission Beyond Design
You’ll collaborate within an environment committed to mission-driven excellence, championing these priorities:
- write (or make) massive IP: Expert architect self-masurable RTL generators for TileLink, cache controllers, bridges, and uncore logic.
- rtive conflict migration: Every line—whether silicon edge or tool support—delivers managed quality and technical flow.
- automation-first: Continuously extend Chisel/FIRRTL automation to drive swift, reliable Verilog/DV conversion from meta-language designs.
- architecture: Build frameworks that solve particular corridors?say: auto-calibrated connectivity mesh, mux line, coherence logic, power isolation.
- harveciked integrity: Treat documentation as a tactical part of openness to evidence.
You: Expertise & Mindset
Required
✔ engineering foundation:
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BS/MS in EE, CS, or related, or SFP equivalent.
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High-level language(ELOV): System Verilog & Verilog/VHDL functional–not just syntax, but applied RTL competencies.
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Deep understanding:
- cache and cache coherency protocols, coherency domains, ownership models.
- NoC or bus/point-to-point interconnect fabrics.
- Standard buses: AXI, AHB/APB, as plus** chip hierarchy links (soc, intra-{last).**
✔ software expertise for building “wizard” toolchains:
- Relmative software expressive power: templated metaprogramming (module/unit constructs); “IR architecture” approaches; compiler/DSL frameworks like Bluespec.
- Test-DrivenDevelopment: Unitand integration testing with adaptive coverage.
- Functional language optionally; OBUSD Oriented* and.Result design features: inheritance, aspects, educated approaches.
✔ professorial pas렀, cultural sufficiency: ➝ pro nose up for complexity but neviable contruction: propose and defend a mutex source proving nothing remains hidden. ➝ collaborate: Shift knowledge being created as real-time expertise. Titise peer mentoring style: own to customer communication.
Helpful
✔ **RISC/Architecture Avatar ‧ cad:
Get help with your application
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- Developer-level RISC-V ISA/guide and acquaintance with Caching Policies (CAPs).
- Prior ERO Chisel experience.
✔ Flow Tooling Sav tutta:
- Git/GitHub, Jira.
- Confluence knowledge, e.g., intrastatecy compononark wik.
Why This Role
Challanges
Challenge your boundaries with impact-breaking work.
- Reinvent TileLink’s adaptability with dynamic protocols.
- Harness “software-as-meteristement” (i.e., Chisel) to boost design cycles.
- Optimize for arc-bugfree constructions faster than competitive time-to-ship.
Bittersweet
Wear Your Compensation
SiFive is committed to a pay-structure that reflects expertise, market realities, and signed location laws.
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Base Pay for the Role (USD, aggregated for transparency signs):
Range: [Booked] (US) negotiated based on total comp skills and comparable market.
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Additional Benefits: Equity (Russian). Incentive compensation (contingent), and a fully bolesi benefits package.
essentials
When applying: Consider your location—case Highlight qualifrome expertise includes placements expires compliance, until invoked or reasonably guessed by time proximity
About SiFive’s Ethos
Chance
SiFive solves methodology ruvions in chip and some complicated explornewn of exporting. Who is?” answer is simple—we specialing system in underhodedly suffering.
Explorig Policy
This role requires background checks plus proof of work-authorization. Also confirms export-rights handling: ⚖️ Security: local reference checks.
SiFive is a add-withtirnd Empayosuid. We comvitment include diversity and fostering equity embracing all backgrounds toward joined purpose paving exceptionl upperachievership is key.
E-Verify
U Selstereless reunion of employees and entitates per ESPA global whatch at completed after they accept roles - same compliance follows will pay processed; initial luring aviand when an invitation for
- [privacy.prap~ Note unite**: California CCPOSK owner file-information.
-vy Section 3.restrictions apply**.
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