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Physical Design Engineer

Cambridge
Posted about 19 hours ago
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I am currently working with an established technology company in Cambridge that develops a range of high-volume computing and embedded products. Due to continued growth, they are looking to hire a Physical Design Engineer to join its expanding team.

This is an excellent opportunity for a Physical Design Engineer to work within a highly collaborative team, contributing across the full chip development lifecycle from early design stages through to silicon delivery and product release. The team is relatively small, giving engineers broad exposure and the opportunity to have a genuine impact on product development.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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The Successful Physical Design Engineer Will Have Experience In

  • The complete physical implementation flow, from netlist through to GDSII
  • Floorplanning, power planning, placement and optimisation, clock tree synthesis, routing and physical verification closure
  • Timing closure and static timing analysis
  • Logic synthesis, equivalence checking and place-and-route methodologies
  • Working on complex ASIC or SoC designs within advanced semiconductor environments

Requirements

  • A strong academic background in Electronics, Electrical Engineering or a related discipline
  • At least two years of industry experience within Physical Design or Physical Implementation
  • A solid understanding of modern ASIC implementation flows and methodologies
  • Strong communication skills and the ability to work effectively within cross-functional engineering teams

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This is a fantastic opportunity to join a company with a strong engineering culture, work on technically challenging products and become part of a close-knit team where your contributions will have a direct impact.

For more information on this opportunity, or other Physical Design positions across the UK and Europe, please contact Jordan Browne.

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Skills

Physical Implementation
Floorplanning
Power Planning
Placement
Optimisation
Clock Tree Synthesis
Routing
Physical Verification
Timing Closure
Static Timing Analysis
Logic Synthesis
Equivalence Checking
Place-and-Route Methodologies
ASIC Design
SoC Design
Semiconductor Environments

Location

Cambridge, England, United Kingdom

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