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Physical Design Engineer – AI Accelerator
An early-stage AI hardware startup in London is building a custom accelerator to support next-generation machine learning workloads. With strong funding in place, they’re growing a small, experienced team to take their chip from concept through to tape-out.
They’re looking for a Physical Design Engineer to play a key role in the implementation of high-performance silicon, working closely with RTL and architecture teams.
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What you’ll be doing:
- Taking ownership of physical implementation from synthesis through to place & route
- Floorplanning, power planning, clock tree synthesis, and timing closure
- Working closely with RTL teams to ensure design for PPA
- Driving signoff activities including STA, IR drop, and DRC/LVS
- Supporting tape-out and silicon bring-up
What they’re looking for:
- Experience in ASIC physical design
- Strong understanding of place & route, timing closure, and physical verification
- Experience with industry standard EDA tools
- Good understanding of digital design and RTL interaction
- Comfortable working in a fast-paced, early-stage environment
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Nice to have:
- Experience working on advanced nodes
- Exposure to high-performance compute, GPUs, or AI accelerators
- Knowledge of low-power design techniques
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