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IC Resources

Principal ASIC Design Engineer

Cambridge
Posted about 18 hours ago
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About the Role

Our client is a highly successful British technology company renowned for designing innovative computing platforms used by millions of developers, educators, engineers, and hobbyists worldwide. With a strong focus on accessible and high-performance computing, the company has established itself as a global leader in embedded and edge computing technologies. As they continue to invest in the development of next-generation silicon platforms, they are expanding their in-house ASIC capability to support an exciting product roadmap.

This role would suit someone who enjoys working autonomously with like-minded people. They have an excellent leadership team and working culture.

The Opportunity

As part of a growing ASIC team, you will play a key role in the development of next-generation silicon products. Working within a small, highly collaborative team, you will gain exposure across the complete silicon development lifecycle, from architecture and specification through design, verification, implementation, test, and product qualification.

This role would suit an experienced IC Design Engineer who enjoys taking ownership, working across multiple disciplines, and contributing directly to the successful delivery of innovative silicon products.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Responsibilities

  • Take ownership of front-end development activities, from specification through design, verification, and implementation
  • Define, specify, configure, and integrate IP and system-level functionality
  • Drive verification planning and execution across complex SoC and MCU designs
  • Collaborate closely with software teams to ensure seamless hardware/software integration
  • Support FPGA platforms used for software development and pre-silicon validation
  • Work alongside implementation teams to resolve timing, power, and physical design challenges
  • Contribute across the wider ASIC development flow to ensure successful product delivery

Requirements

  • Typically 10+ years’ experience in SoC or MCU architecture and design
  • Proven experience delivering at least one successful silicon tape-out where you held architectural ownership of a complete chip or significant subsystem
  • Deep understanding of modern microcontroller and processor architectures, including:
    • Real-time operation and deterministic interrupt handling
    • Low-power architectures
    • Flash and SRAM hierarchies
    • Common peripheral interfaces such as SPI, I²C, UART, USB, ADC/DAC, timers, and programmable I/O fabrics
  • Strong knowledge of broader SoC architecture, including:
    • AXI, AHB, and APB interconnects
    • Cache hierarchies
    • DMA and memory controllers
    • Security architectures
    • Integration of operating system-class subsystems alongside real-time domains
  • A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints.
  • Familiarity with scripting languages such as Bash, Python, or Tcl.

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Please note that this role is based in Cambridge and requires full-time onsite attendance.

This opportunity offers a fantastic compensation package and a number of non-monetary benefits. This is a great opportunity to join them as they leap into their next growth phase.

For more information, please contact Rachel Mason at IC Resources

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Skills

SoC Architecture
MCU Design
Silicon Tape-out
Microcontroller Architectures
Real-time Operation
Low-power Architectures
Flash Hierarchies
SRAM Hierarchies
Peripheral Interfaces
RTL Design
Verification Methodologies
Scripting Languages
Timing Closure
Power Analysis
Physical Design

Location

Cambridge, England, United Kingdom

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