Elite People Partners Ltd
Principal Design Engineer
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Principal Design Engineer
Principal Design Engineer (SystemVerilog / Micro-Architecture) – £100,000–£135,000 + bonus
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My client’s engineering team is seeking a Principal Design Engineer to enhance the development of cutting-edge GPU / AI compute IP. This role focuses on strengthening core micro-architecture and system design capabilities within critical programmes.
About the Role
A multi-disciplinary position operational at the interface of architecture design, RTL design (SystemVerilog), and physical implementation. The successful candidate will collaborate closely with Verification and Systems teams, ensuring highly-scalable, high-performance silicon delivery.
Responsibilities
- Own and drive end-to-end micro-architecture definition from concept specs
- Develop high-quality SystemVerilog RTL to meet strict performance-power-area goals
- Ensure design-for-verification (DFV) efficiency alongside verification teams
- Collaborate with physical design teams to resolve timing, congestion, and power challenges
- Shape overall design strategies for GPU / compute IP blocks
- Champion complex architectural elements and technical direction
- Proactively influence engineering excellence within a matrix organisation
- Operate as a senior technical leader, driving impact on high-value IP programmes
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Essential Skills
✅ Proven expertise in SystemVerilog RTL design (12+ years) ✅ Ownership of micro-architecture (beyond just implementation) ✅ ~15+ years digital design experience in SoC/CPU/GPU or ASIC environments ✅ Physical design depth (awareness of timing/area/power tradeoffs) ✅ Verification and DFT methodology awareness (DFT-related) ✅ Experience working across architecture·verification·physical teams in collaborative settings
Nice to Have (but not required)
✨ GPU / CPU / AI accelerator block design experience ✨ Memory/caches/interconnect design expertise ✨ Datapath/ALU/compute pipeline microarchitecture domain knowledge ✨ High-performance SoC environments understanding
This role is NOT:
- Pure “coding” at RTL level without architectural ownership
- Block-contained implementation (deeply integrated with larger architectures)
- Research-focused (expect hands-on loading work)
- Fully prescriptivedan direct hire
Why Join Us
✅ Lead at Principal level with trailblazing impact ✅ Drive real timeline unblocking on core IP programmes ✅ Shape breakthrough designs in GPU/AI computing ✅ Engage in high-visibility collaboration across teams ✅ Access to architecture·system·design frontiers
Compensation & Benefits
| Offer Detail | Summary |
|---|---|
| Base Salary | £100,000–£135,000 |
| **Bonus | £35K–£40.6K (30% target) |
| Total Compensation | £135K–£175.5K |
| Pension | Company contribution + salary-matching |
| Medical | Private medical insurance |
| Protection | Critical illness and income protection services |
| Relocation | Fully supported |
| Flexible Work | Hybrid-remote 3 days onsite |
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Interview Process
3-Step Process (completed within 2–3 weeks)
- Technical Screening (45-min) – Coding/architecture discussion
- Technical Panel (120 min) – Deep dive in micro-arch+design strategies
- HR/CTO Alignment – Ledgers final cultural and stakeholder fit
Note: opens immediately—impact visible upon start.
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