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Aion Silicon

Principal Design Engineer

African Quarters
Posted about 15 hours ago
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Location: Global (Hybrid)

Department: Engineering

Reporting to: Frontend Design Function Lead

At Aion Silicon, we're tackling some of the most complex and exciting challenges in ASIC and SoC design. As we continue to grow, we're looking for an exceptional Principal Design Engineer to provide technical leadership across cutting-edge silicon development programmes, working with global customers and world-class engineering teams. This is more than a design role. It's an opportunity to influence technology strategy, mentor talented engineers, drive innovation, and play a key role in delivering advanced semiconductor solutions from concept through to silicon.

Why This Role?

As a Principal Design Engineer, you'll be at the forefront of complex ASIC and IP development projects, leading multidisciplinary teams across multiple locations. You'll work directly with customers, architects, and technology partners to create innovative solutions that power the next generation of semiconductor products. You'll have the autonomy to make technical decisions, shape methodologies, influence engineering direction, and help define best practices across the organisation.

What You'll Do

  • Lead the technical delivery of complex ASIC and SoC development programmes.
  • Define microarchitectures and translate customer requirements into high-quality silicon solutions.
  • Drive frontend design activities from specification through integration and handover.
  • Mentor and develop engineering teams, fostering a culture of technical excellence.
  • Collaborate with customers, architects, and third-party IP providers to solve complex design challenges.
  • Guide methodology development and continuous improvement initiatives.
  • Evaluate and deploy industry-leading EDA tools and design flows.
  • Manage technical risks, schedules, deliverables, and quality targets.
  • Represent Aion Silicon within the wider engineering community through conferences, technical papers, and industry engagement.

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What We're Looking For

Essential

  • 10+ years' experience in digital IC, ASIC or SoC design
  • Deep understanding of digital design concepts and complex system architectures
  • Proven track record of technical leadership on large-scale semiconductor projects
  • Experience leading engineers and influencing technical direction
  • Strong problem-solving and decision-making skills
  • Customer-facing experience with the ability to communicate complex technical concepts clearly
  • Experience with project and task management tools such as Jira
  • Degree, Master's, or PhD in Electronic Engineering, Computer Engineering, or a related discipline (or equivalent experience)

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Desired

  • Experience Verilog, SystemVerilog or VHDL
  • Design for Test (DFT)
  • Clock, reset and power management architectures
  • UPF / CPF power intent
  • Lint, CDC and design sign-off methodologies
  • Synthesis and timing constraints generation
  • SoC verification and HW/SW co-verification
  • Linux environments and scripting with Python, Tcl, Perl or Java

Why Join Aion Silicon?

At Aion Silicon, we combine the agility of a specialist engineering organisation with the opportunity to work on globally significant semiconductor projects. Our engineers collaborate with some of the most innovative technology companies in the world, developing products that push the boundaries of performance, power efficiency, and innovation. You'll join a culture that values:

✅ Technical excellence

✅ Innovation and creativity

✅ Collaboration and knowledge sharing

✅ Career development and leadership growth

✅ Global teamwork and customer impact

If you're passionate about leading complex silicon design programmes and want to work alongside some of the brightest minds in the industry, we'd love to hear from you. Apply today and help design the technology powering tomorrow.

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Skills

ASIC Design
SoC Design
Digital IC Design
Technical Leadership
Microarchitecture Definition
Verilog
SystemVerilog
VHDL
Design for Test (DFT)
Power Management Architectures
UPF/CPF
Lint/CDC
Synthesis
Timing Constraints
SoC Verification
Python

Location

Asiago, Veneto, Italy

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