SiFive
Principal Interconnect Design Engineer
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Principal Interconnect Design Engineer
Principal Hardware Engineer – TileLink & CPU Interconnect IP Architects
SiFive
About SiFive
The pioneers who introduced RISC-V to the world, SiFive is reshaping the future of compute by unlocking RISC-V’s potential for high-performance, data-centric applications. Our cutting-edge compute platforms empower leaders across AI/ML, automotive, data centers, mobile, and consumer markets. By fusing innovation with collaboration, we design customizable IP that accelerates time-to-market—transforming industries, one processor at a time.
At SiFive, we thrive on bringing world-changing ideas to life. Our success is built on diverse, talented teams who innovate tirelessly and share knowledge openly. Ready to help build the future?
The Role
SiFive seeks a principal-level hardware engineer passionate about designing next-generation CPU and interconnect IP, propelling RISC-V as the architecture of choice for SOCs. We focus on creating massively configurable IP and revolutionizing hardware design by adopting software-driven methodologies (Chisel/Scala).
Join us to advance our TileLink interconnect, cache controllers, and uncore infrastructure, enhancing configurable generators beyond current limitations.
The Challenge
- Architect world-leading interconnect and protocol IP on RISC-V and TileLink architectures
- Master the art of domain-specific language (DSL) hardware generation (Templated metaprogramming, compiler-based approaches)
- Work at the intersection of software engineering and hardware design in an agile, high-performance environment
- Collaborate to define cache coherence protocols, multi-core scaling, and hierarchical interconnect solutions
Responsibilities
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IP Development & Architecture
- Design and implement RTL generators in Chisel for TileLink interconnects, cache controllers, and protocol bridges (AXI, AHB, UCIe, etc.)
- Build self-configuring systems where interconnect elements adaptively connect via dynamic generators
- Drive multi-core/multi-system coherence optimizations to deliver higher performance and efficiency
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Software-Driven Hardware
- Refine generators with extensive configurability as a first-class design principle
- Integrate new IP into SiFive’s Chisel/FIRRTL framework and contribute to its ongoing improvements
- Develop tools for automated documentation, verification testbenches, and packaged software generation
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Verification & Collaboration
- Lead initial validation in development sandboxes and collaborate with the verification team to define test plans
- Champion knowledge sharing through documentation and active participation in technical design discussions
What You Bring to the Role
Technical Competencies
- Deep understanding of cache architectures and cache coherence protocols
- Proven experience with network-on-chip (NoC) or high-performance interconnect fabrics
- Proficiency in AXI, AHB, APB, CHI, CXL, UCIe, or similar bus protocols
- Strong background in software engineering (OOP, FP, AOP, functional paradigm, compiler design)
- Experience with templated metaprogramming and DSLs for hardware description
- Familiarity with HDL (Verilog, SystemVerilog, VHDL) and RTL design methodologies
- Knowledge of hardware verification techniques (e.g., SystemVerilog simulations, formal verification)
Cultural Fit
- Exceptional detail-oriented problem-solving mindset
- Belief that engineering thrives in collaboration, with an appetite for team sport mentality
- Willingness to tackle complex, open-ended challenges
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Qualifications
- BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline
- Equivalent experience for self-taught candidates (portfolios and demonstrably advanced projects welcome)
Nice-to-Haves
- Experience with Scala/Chisel, Bluespec, or other configurable DSLs
- Knowledge of RISC-V architecture (IRC/architecture internals)
- Familiarity with dev tooling (Git/GitHub, Jira, Confluence)
Pay & Benefits
SiFive values transparency and equity in compensation. Base Pay Range: $231,444.00 - $282,876.00
Additional compensation may include:
- Variable/performance-based incentives
- Equity awards
- Comprehensive benefits package (healthcare, retirement, paid time off, and more)
Note: Pay varies by location and reflects market considerations.
Additional Considerations
- Biometric and background checks required.
- This role is contingent on compliance with U.S. export control regulations (valid authorization to work with or obtain access to export-controlled technology).
SiFive is committed to fostering a diverse, inclusive workplace. We celebrate differences and affirm that our technology-driven culture thrives on idea-sharing and cross-functional collaboration.
If you’re excited to add depth and impact to the future of computing, join us. We’re building more than chips—we’re shaping a world where no economic barrier limits innovation.
Ready to make an impact? Apply to help drive the next wave of technical revolution.
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