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RTL Design Engineer - CPU / Low-Power / High-Performance

Cambridge
Posted about 22 hours ago
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RTL Design Engineer - CPU / Low-Power / High-Performance

We are currently partnered with an industry-leading semiconductor giant in the UK looking to expand their team in the UK with an experienced RTL Design Engineer to work on the development of high-performance, low-power CPU cores for the next generation of premium mobile and IoT devices.

This is a permanent position in Cambridge. Please note, this is a fully onsite role.

Key Responsibilities

  • Collaborate with the modeling team to explore and implement high-performance CPU strategies.
  • Transform high-level architectural research into detailed, implementable technical specifications.
  • Design, assess, and refine RTL (Verilog/VHDL) to hit aggressive timing, area, and power goals.
  • Partner with the DV team to ensure the design meets both functional correctness and performance benchmarks.
  • Work with physical design teams to validate timing, reliability, and testability for tape-out.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Key Requirements

  • Thorough knowledge of areas like Instruction Fetch/Decode, Out-of-Order Execution, and Memory Subsystems.
  • Strong proficiency in Verilog and/or VHDL and waveform debugging.
  • Solid understanding of logic design principles and their implications on timing and power.
  • Understanding of register renaming, instruction scheduling, and speculative execution.
  • Experience using Python or Perl for design automation and analysis.

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Keywords: CPU Design / RTL Engineer / Verilog / VHDL / Micro-architecture / Out-of-Order Execution / Low Power Design / PPA / Instruction Fetch / Logic Design / Python / Perl / Cambridge / Semiconductor

If you are interested in this RTL Design Engineer position, please send a CV to ts@eu-recruit.com

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Skills

RTL Design
Verilog
VHDL
CPU Design
Low Power Design
Micro-architecture
Out-of-Order Execution
Instruction Fetch
Instruction Decode
Memory Subsystems
Logic Design
Register Renaming
Instruction Scheduling
Speculative Execution
Python
Perl

Location

Cambridge, England, United Kingdom

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