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Senior Analog IC Design Engineer – flexible hybrid

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Senior Analog IC Design Engineer – flexible hybrid
Senior Analog IC Design Engineer – Southampton (Hybrid)
Location: Southampton (with hybrid flexibility)
Our scaling semiconductor client is looking for a Senior Analog IC Design Engineer to help shape a revolutionary technology – ultra-low-power optical interconnects for AI systems.
This rare and impactful role sits at the intersection of:
- High-speed analog design
- Photonics integration
- Advanced CMOSdevelopment
You’ll lead the complete IC development lifecycle—from circuit design and verification through tape-out, silicon characterisation, testing, and product commercialisation.
Key Responsibilities
- Design and optimise analog circuits for a new class of ultra-low-power optical links, ensuring high-speed performance.
- Take ownership of full IC development, from initial architecture design to tape-out and post-silicon validation.
- Collaborate with cross-functional teams (e.g. photonics and digital design) to refine specifications and drive product success.
- Work seamlessly in a fast-moving, high-tech environment, balancing creativity with rigorous engineering discipline.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
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Required Experience & Qualifications
You should have: ✔ A Masters or PhD in Electrical Engineering (or a related field). ✔ Comprehensive experience in analog/mixed-signal/RF IC design across the full flow:
- Spec-to-architecture
- Detailed schematic design
- Bench testing and lab validation
- High-volume production scaling ✔ Deep expertise in deepp-submicron CMOS node technologies (e.g. 28nm, 16nm, or modern FinFET). ✔ A strong track record in circuit verification and debug before tape-out. ✔ An ability to learn swiftly and contribute effectively in a collaborative team environment.


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Desirable (but not essential): ▶ Significant experience in high-speed design (e.g. for data conversion or IO applications).
What’s Offered
- Competitive base salary + substantial bonus package
- Flexible hybrid working—onsite once every fortnight if required
- Relocation assistance (if needed)
- The chance to work on cutting-edge technology at the forefront of AI and optical communication
For more details, contact:
Caroline Pye IC Resources [No direct details provided]
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