IC Resources
Senior Design Verification Engineer

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I am seeking a Senior Design Verification Engineer to join an established and fast-growing startup as it enters its next phase of growth. With a team of nearly 100 people, this company is at the forefront of post-quantum cryptography, developing security-critical technologies with global impact.
You will play a key role in verifying highly secure designs, working closely with experienced engineers in a collaborative, high-trust environment.
What you’ll be doing
As part of the verification team, you will:
- Build and extend UVM testbenches to verify cryptographic IP and subsystem designs
- Develop Python-based tools and automation to improve verification efficiency and productivity
- Apply formal verification techniques in creative and effective ways
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Beyond hands-on verification, you will also:
- Influence and define verification methodologies and strategies
- Architect testbenches using UVM and formal-based approaches
- Define verification plans, functional coverage models, and test strategies at block and subsystem level
- Lead verification for IPs or subsystems, including effort estimation, scheduling, task allocation, and progress reporting
- Drive coverage closure and sign-off quality across complex designs
- Mentor junior engineers and help raise the overall capability of the team
Required experience
- Strong background in UVM-based verification at IP and subsystem levels
- Proven experience building UVM testbenches from scratch
- Proficiency in Python for verification automation
- Solid experience with SystemVerilog Assertions (SVA)
- A minimum of 4 years experience.


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What’s on offer
- Competitive base salary plus share options
- Opportunity to help build something from the ground up in a growing, mission-driven company
- Fully remote role (must be based at a UK address) OR be an EU National.
- Visa sponsorship available
This role will suit someone who thrives in small, collaborative teams, communicates clearly, and is passionate about delivering high-quality verification for security-critical systems.
Contact Rachel Mason for more information.
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
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