IC Resources
Senior Design Verification Engineer
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Great opportunity for a Senior Staff Verification Engineer to join a global R&D network.
As a Staff Verification Engineer, you will take ownership of IP verification topics for cutting-edge designs of the future of the company’s Automotive division, while working together with the team who has a proven track record in successful IP deliveries into Automotive Microcontrollers.
Responsibilities
- Define a verification plan, requirements mapping, develop an SV-UVM test bench and solve related potentially complex problems
- Debug failing test cases to root cause
- Define and write a functional coverage model
- Participate in reviews to ensure test bench meets quality and sign-off targets, including coverage, functional safety and test bench qualification
- Proactively help increase efficiency of verification activities and mitigate risks early
- Contribute to enhancing Verification strategy and architecture of IP test benches
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Requirements
- At least 5 years of experience in verification, with IP level as mandatory and Subsystem level as an advantage
- Expertise in hardware verification languages, particularly System Verilog and UVM, with the ability to design efficient and effective test bench architectures
- Familiarity with EDA tools for Design and Simulation, as well as scripting languages such as Python or Perl
- Knowledge of functional safety standards, including ISO26262 and ASIL-D requirements
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For more information and a confidential discussion, please contact Rachel Mason at IC Resources.
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