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Senior DFT Engineer

Cambridge
Posted about 14 hours ago
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DFT Engineer for ASIC Designs

In this role, you will be responsible for creating, implementing, and verifying DFT solutions for future ASIC designs, ensuring that quality standards are upheld for products shipping in volume. You will leverage advanced DFT methodologies to optimize test coverage, cost, and time-to-market. This position is office-based in Cambridge and visa can be considered for exceptional candidates only!

Responsibilities

  • Define and implement DFT strategies at the chip, subsystem, and IP levels, balancing structural and functional methods while making pragmatic trade-offs
  • Utilize Tessent DFT tool flows for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL in both flat and hierarchical designs
  • Verify DFT structures and debug related issues to ensure robust design implementation
  • Support DFT processes through implementation and sign-off, including generating timing constraints and resolving timing, power, and formal equivalence issues

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Qualifications

  • A degree in electronic engineering, computer science, or a related discipline plus at least 5 years industry experience in DFT Engineering
  • Proven experience with IC development flows
  • Proficiency with Tessent DFT tools
  • Strong understanding of complex IP issues related to DFT, including on-chip clocking
  • Hands-on experience in ATPG, MBIST, and simulation debugging, including UPF-related issues
  • Proficiency in scripting, particularly TCL

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If you are a dedicated professional with a passion for DFT engineering and a desire to contribute to cutting-edge ASIC development and want to know more about this opportunity, please contact Ane @ IC Resources with your CV and a time for an initial call.

Priority will be given to applications from within the UK followed by EU.

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Skills

DFT Engineering
Tessent DFT Tools
IC Development Flows
ATPG
MBIST
Simulation Debugging
Scripting
TCL
On-Chip Clocking
DFT Strategies
Debugging
Timing Constraints
Power Issues
Formal Equivalence
Hierarchical Designs
Flat Designs

Location

Cambridge, England, United Kingdom

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