Yoh, A Day & Zimmermann Company
Senior FPGA Design Engineer

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Senior FPGA Design Engineer – Build Tech That Will Orbit the Earth
📍 Southampton (Hybrid – 2 days onsite)
💰 Circa £70k + Bonus + Equity + Private Medical + Pension
Satellites are getting smarter. This company is building the signal processing hardware that’s making it happen.
They’re tackling one of the toughest problems in mobile communications: putting full 5G base stations in orbit. That means power-efficient, high-throughput digital signal processing running on space-qualified devices—and they’re looking for another FPGA expert to help make it real.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
This is a hands-on role focused on RTL development and integration of complex IP blocks targeting both FPGA and ASIC. You’ll work across the full development flow: writing Verilog/SystemVerilog, working on timing closure and synthesis, and helping with system integration and lab validation. You’ll also be collaborating closely with other engineers—from algorithms to verification.
The ideal background? Real-time, high-speed FPGA design. Signal processing knowledge is a bonus. UVM, Python scripting, or experience with AMBA protocols? Even better.


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Why this role?
- Because it’s not every day you get to work on tech that literally leaves the planet.
- The team is smart, the mission is bold, and the culture is engineer-led.
- You’ll have space to contribute, solve hard problems, and see your work make it to orbit.
If that sounds like your kind of challenge, we’d love to speak.
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