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Senior FPGA Design Engineer

Cambridge
£70k – £100k/yr
Posted about 20 hours ago
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Senior FPGA Design Engineer | Hybrid | Cambridge

Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative engineering team, contributing to the core FPGA technology that powers a range of next-generation products.

Responsibilities

  • Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
  • Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
  • Write module specifications, review code and documentation, and maintain high engineering standards.
  • Collaborate with hardware, software, and mechanical engineers to deliver new products to market.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Only hits

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Essential Experience

  • Strong SystemVerilog FPGA design experience.
  • RTL verification skills and familiarity with Python.
  • Experience writing timing constraints and achieving timing closure.

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Desirable Experience

  • Experience with cocotb for FPGA verification.
  • Familiarity with Linux command line, Git/SVN, and Markdown.

Do you want to work in a high variety, high complexity environment on highly advanced systems? Apply with your CV & I'll be in touch.

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Skills

SystemVerilog
FPGA Design
RTL Verification
Python
Timing Constraints
Timing Closure
Cocotb
Linux
Git
SVN
Markdown

Location

Cambridge, England, United Kingdom

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