Platform Recruitment
Senior FPGA Design Engineer

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Senior FPGA Design Engineer | Hybrid | Cambridge
Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative engineering team, contributing to the core FPGA technology that powers a range of next-generation products.
Responsibilities
- Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
- Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
- Write module specifications, review code and documentation, and maintain high engineering standards.
- Collaborate with hardware, software, and mechanical engineers to deliver new products to market.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Essential Experience
- Strong SystemVerilog FPGA design experience.
- RTL verification skills and familiarity with Python.
- Experience writing timing constraints and achieving timing closure.


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Desirable Experience
- Experience with cocotb for FPGA verification.
- Familiarity with Linux command line, Git/SVN, and Markdown.
Do you want to work in a high variety, high complexity environment on highly advanced systems? Apply with your CV & I'll be in touch.
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