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Senior FPGA Engineer

Cambridge
£90k – £130k/yr
Posted 1 day ago
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Senior FPGA Engineer

Senior FPGA Engineer | £100-180k | Cambridge

This is an opportunity to join a global team developing ultra-low latency technology.

You will oversee all aspects of FPGA system design, driving advancements to ensure my client maintains its technological advantage by building the next generation of infrastructure.

Responsibilities

  • Architecting and implementing RTL designs on high-end FPGAs (Xilinx / Intel).
  • Performing simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems.
  • Leading the definition of micro-architectures and verification environments.
  • Driving technical excellence across the FPGA team through mentorship and code reviews.
  • Collaborating with firmware, software, and infrastructure teams to optimise full-stack performance.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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It searches the market for you

Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.

Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

Only hits

No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.

Requirements

  • 7+ years’ FPGA / RTL design experience in timing-critical systems.
  • Strong background in SystemVerilog, synthesis, timing closure, and verification.
  • Hands-on experience with Vivado / Quartus or equivalent toolchains.
  • Familiarity with AXI, PCIe, Ethernet, or custom high-speed interfaces.

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Bonus Skills

  • Exposure to high-performance computing, networking, or real-time data systems.
  • Knowledge of C/C++ or Python for tooling, verification, or firmware collaboration.
  • Appreciation for hardware–software co-design and system-level optimisation.

Apply now to join a global leader in an extremely high growth market!

Platform Recruitment: We cover a wide range of IT and Engineering positions, including C++, Embedded, Electronics, Mechanical, DevOps, Cloud, Support, Project Management, Technical Sales, and more.

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Skills

FPGA Design
RTL Design
SystemVerilog
Synthesis
Timing Closure
Verification
Vivado
Quartus
AXI
PCIe
Ethernet
High-Speed Interfaces
C/C++
Python
Hardware-Software Co-Design
System-Level Optimisation

Location

Cambridge, England, United Kingdom

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