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Infineon

Senior Verification Engineer (f/m/div)

Bristol
Posted about 1 month ago
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#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Your Role

Key responsibilities in your new role:

In this role, you will contribute to the development of System Verilog - UVM test benches, debug test cases, and understand functional coverage models, working closely with senior engineers.

Assist in developing and maintaining System Verilog - UVM test benches in collaboration with senior engineers and the team Contribute to creating and enhancing SV UVM verification components, with guidance and supervision from experienced team members Support debugging failing test cases to identify root causes, gaining experience with debugging tools and best practices Assist with defining functional coverage models and ensuring coverage goals are achieved under guidance Participate in team reviews, design discussions, and process improvements, contributing your ideas and learning from team members Help ensure test bench quality and sign-off targets are met, including coverage metrics and functional safety requirements

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Your Profile

Qualifications and skills to help you succeed:

A Bachelor's degree in Electrical/Electronic Engineering or a related field At least 1-2 years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience) A strong understanding of basic Verification concepts, System Verilog design and testbench fundamentals Eagerness to learn and apply industry-standard verification methodologies like UVM Understanding of debugging workflows and a willingness to learn how to use tools to debug and analyze test issues Strong problem-solving skills, collaborative mindset to work effectively in a team and ability to manage your time effectively Fluency in English (mandatory)

Please send us your CV in English.

Contact: Rita Costa, LinkedIn

#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

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We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

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Skills

System Verilog
UVM
Verification Engineering
Functional Coverage Models
Debugging
Problem Solving
English Fluency

Location

Bristol, England, United Kingdom

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