Senior/Principal Physical Design Engineer

Senior / Principal Physical Design Engineer

Fractile is building the silicon, systems and software to break through the memory wall, the fundamental hardware constraint standing between today's AI and what comes next.

The frontier of AI is no longer a research problem. The tasks AI can complete are doubling in complexity every six to seven months and the tokens required to complete them are scaling with it. Sequential reasoning, the kind that can't be parallelised away, means the internal clock speed of inference systems is the critical constraint. What stands between where we are today and the future potential of AI isn't smarter algorithms; it's the hardware to run them fast enough to matter.

Today's chips are hitting their wall. We're building the ones that don't.

Fractile is seeking to increase the clock speed of global progress, one chip at a time.

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities

Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution. Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics. Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques. Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others. Interface with foundries and process engineers to ensure manufacturability and yield optimisation. Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design. Work with advanced AI tools and models to improve productivity, analysis, and design quality.