Axelera AI
Senior/Staff Engineer - Computing Architecture
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Senior/Staff Engineer - Computing Architecture
About Axelera AI
Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to empower humanity and advance the world around us.
In just four years, we have:
- Raised $370 million
- Built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), representing 18+ countries
- Operate from offices in Belgium, France, Switzerland, Italy, and the UK
- Headquartered at High Tech Campus, Eindhoven, Netherlands
- Launched the Metis™ AI Platform, delivering:
- 3-5x efficiency and performance improvements
- Visibility into target business pipelines exceeding $100M
Our relentless focus on innovation has positioned us as a global leader in the AI industry.
Open To Opportunity!
Are you up for the challenge?
Position Overview
Axelera AI seeks a Senior/Staff Engineer – Computing Architecture to architect and develop the next-generation edge-to-cloud AI computing systems. This role demands close collaboration with hardware, software, and product teams to define architecture requirements, engineer for high performance, and ensure scalability within our rapidly evolving solutions.
Key responsibilities include:
- Defining and developing cutting-edge architectures for AI hardware accelerators (NPUs, FPGAs, programmable hardware, etc.).
- Analysing and optimizing computational workloads to deliver:
- Maximised performance
- Lowest possible power consumption
- Highest efficiency for AI applications (inference, training, and hybrid workflows).
- Driving innovation through rigorous evaluation of emerging technologies, industry trends, and multidisciplinary research.
- Translating system requirements into holistic architectural designs that balance performance/cost/power trade-offs for hardwareтальylate systems-and-software teams.
- Building simulation and modelling tools to validate designs before hardware first prototypes arrive.
- Mentoring junior engineers, fostering a culture of technical excellence and stimulating an experiment-driven atmosphere.
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Key Responsibilities
Architecture Roadmapping
- Lead AI computing architecture design, spanning high-level conceptualisation to implementation.
- Align with McPAT/GPUcast/NVProfit-like tools and quantify performance across diverse AI synapses.
Energy-Efficient AI Accelerators
- Optimise low-level computations (e.g. Matrix Multiplication Kernels, Hardware-Aware SOTA Precisions).
- Promote innovative use cases in:
- Embedded AI systems
- Data-centre-scale MLOps
- ONNX-compatible inference engines.
Cross-Industrial Collaboration
- Cooperate with:
- FPGA architecture domain leaders (Xilinx, Lattice)
- ASPV/LTPV hardware-compiler communities
- Applied researchers from 500M-million inbound pipeline projects.
Technical Leadership
- Evaluate and experiment with emerging hardware trends:
- Scatter Cache Architecture (SCA), CRebro/dPronte alternatives.
- Depthwise-Multiplication-Aware SynaOps
- Build and verify open-source tooling for future-proof architecture performance models.
Mentorship & Culture Building
- Accelerate team growth by fostering peer-driven improvement cycles.
- Advocate best practices through:
- Code reviews
- PhD externship exchanges
- Global workshop training programs.
Qualifications
Essential
- Degree in Computer Engineering, Electrical Engineering, or closely related field (Master's or higher).
- 5+ years of practical expertise in architectural design, preferably within:
- AI accelerators
- Semiconductor firms
- Large-scale computing systems.
- Expertise in AI hardware architectures, with deep familiarity of:
- Neural Processing Units (NPUs)
- GPUs and programmable hardware (RTLs, FPGA fabrics).
- Proficiency in: Architectural simulation (DSEntstudio), FPGAs (e.g. OpenCl, CUDA), Tullis optimization.
- C++/Python (deep understanding of SLiM, Rust failure amenities, or similar) & profiling (e.g. VMProfil).
- Strong reference with chip metrics pipeline.
- Demonstrable track record: peer-reviewed publications or *h2-hand Industry milestones.
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Preferred Enhancers
- IC cleanroom design level experience (preferred: RTL-level simulations, DSEkrit stages).
- CUDA/OpenCL-supported parallel multicore protocols + Single-Instruction stacks.
- Hands-on code-level hardware agility: RISC-V ASUvers, or protocol-sensitive concepts (ABC, MPW, etc.).
- Collaborative experience with MLIR framework or TVM/Tensorflow.synthetic railways.
Location
Axelera AI supports flexible work arrangements. Candidates may either:
- Relocate to any of our global offices (in city clusters):
- Belgium: Leuven.
- Netherlands: Amsterdam or Eindhoven.
- Switzerland: Zürich.
- Italy: Florence or Milan.
- UK: Bristol (where you are already living).
- Remotely from any EU jurisdiction, including the UK.
Priority given to candidates relocating to Belgium or Italy.
What We Offer
Join a fast-growing technology business where your brilliance can revolutionise what’s possible, not just in AI, but across industries. We offer:
Compensation
- Cutting-edge benefits package, including:
- Pension plan
- Insurance coverage (healthcare, life, etc.)
- Equity options via company shares
Culture
- An open, collaborative team dynamic.
- Champions calibrated self-possession and merit-based equitability.
- Medium-lead opportunities and proactive mentorship.
Inclusivity
- Fully committed to an unbiased, diverse workplace:
- Advances universal representation driven by impact, merit.
- Encourages team members worldwide to embrace gender non-conformity for technical harmony.
- Quick-and-meritorious considerations towards internationally varied backgrounds.
Ready To Shape AI’s Future?
If you envision yourself breaking boundaries in AI computing systems, let’s connect. Send your CV (one page is preferred) and Computing Architecture portfolio, and apply now! 🌐
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Jessica, London
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