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Server CPU Physical Design Engineer - ASIC / CPU Design / Physical Implementation / Semiconductor
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Server CPU Physical Design Engineer - ASIC / CPU Design / Physical Implementation / Semiconductor
We are currently partnered with a leading semiconductor technology company developing next-generation high-performance server processors for advanced computing applications. As part of their continued growth, they are looking to hire a Server CPU Physical Design Engineer to contribute to the implementation and optimisation of cutting-edge CPU designs from RTL through to GDSII.
Key responsibilities
- Own or contribute to CPU block implementation from RTL/netlist through to GDSII, including synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimisation, ECO implementation, and sign-off.
- Drive timing closure across multiple operating modes, process corners, and performance conditions.
- Deliver high-performance, low-power CPU designs that meet aggressive power, performance, and area (PPA) targets.
- Debug and resolve complex implementation challenges relating to timing, congestion, clocking, routing, IR drop, power integrity, electromigration (EM), ECO closure, DRC/LVS, and physical verification.
- Collaborate closely with architecture, RTL, circuit design, CAD, SoC, verification, and post-silicon teams to optimise implementation quality and product performance.
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Key requirements
- Strong commercial experience in ASIC or CPU physical design implementation.
- Proven expertise in synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, ECO implementation, and physical sign-off.
- Strong understanding of static timing analysis (STA) and timing closure methodologies across complex semiconductor designs.
- Experience balancing timing, power, area, congestion, and routability to achieve optimal PPA.
- Knowledge of high-performance and low-power physical implementation techniques.
- Hands-on experience with industry-standard EDA tools such as Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal, or equivalent.
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Keywords
Server CPU Physical Design Engineer / Physical Design Engineer / ASIC Physical Design / CPU Design / Semiconductor / RTL-to-GDSII / Physical Implementation / Place and Route / P&R / Floorplanning / Clock Tree Synthesis / CTS / Timing Closure / Static Timing Analysis / STA / ECO / Physical Sign-Off / PrimeTime / Tempus / Innovus / Genus / Fusion Compiler / Voltus / RedHawk / Conformal / Physical Verification / DRC / LVS / IR Drop / Electromigration / EM / Low Power Design / High Performance Computing / HPC / Server Processors / Silicon Engineering / Python / Tcl / Perl / VLSI
If you are interested in this position, please send your CV to Alistair@eu-recruit.com
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