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Genoa Ventures

Silicon Architect

City of London
$234k – $298.3k/yr
Posted about 18 hours ago
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Location

New York City; London

Employment Type

Full time

Location Type

On-site

Department

Hardware

Compensation

$234,001 – $298,252
Offers Equity

We are committed to competitive and equitable compensation based on role, skills, and experience. Salary ranges are guidelines, with final compensation varying by role, experience, and location and reviewed regularly for fairness.


Overview

Application

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.


The Role

Most accelerator architecture is refinement: a known substrate, a known programming model, decades of prior art to lean on. This seat is not that. Normal's silicon computes with stochastic analog dynamics in memory, and the architecture that exploits it is being discovered alongside the work.

As our Silicon Architect, you will own the architecture of its compute blocks: the core decisions that determine how Normal's silicon actually computes, working directly with our Systems Architect, research and engineering leadership, and the AI platform team whose tools you'll use to design it. This is a seat for someone who wants to define structures no prior art covers, and who has the architecture-to-silicon range to defend them all the way to tapeout.


What You'll Own

  • Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do.
  • Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it.
  • Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
  • ISA Co-Design: Partner with the compiler lead on ISA co-design. The compute tile must be compilable and programmable, not just simulatable. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
  • Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions are answered in FPGA versus cycle-accurate simulation, define what each prototype must prove, and partner with our FPGA Design Engineer, who owns implementation and bring-up, to de-risk decisions before tapeout. System-level validation is owned by our Systems Architect.
  • Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, not just consume.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

Start with a chat, not a search bar

Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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It searches the market for you

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Only hits

No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.


What Makes You a Great Fit

  • A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
  • Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped the structures inside a chip, not just consumed them from the outside.
  • Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
  • Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot.
  • Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level.
  • Experience writing microarchitecture specifications and working closely with RTL engineers through implementation. Your specs are read, not just filed.
  • Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
  • Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it.

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Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.


Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.


Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.


Compensation Range: $234,001 - $298,252

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Skills

Silicon Architecture
Microarchitecture
AI Accelerators
Hardware Specification
FPGA
Python
C++
SystemVerilog
Workload Analysis
Datapath Design
Simulation
Quantization
Reduced-Precision
PPA Tradeoffs
ISA Co-Design
Pre-Silicon Validation

Location

City of London, England, United Kingdom

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