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STA Engineer

Cambridgeshire
Posted 1 day ago
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STA Engineer

STA Engineer - Cambridge

I am currently working with an established technology company in Cambridge that develops a range of high-volume computing and embedded products. Due to continued growth, they are looking to hire a STA Engineer to join its expanding team.

This is an excellent opportunity for a STA Engineer to work within a highly collaborative team, contributing across the full chip development lifecycle from early design stages through to silicon delivery and product release. The team is relatively small, giving engineers broad exposure and the opportunity to have a genuine impact on product development.

The successful STA Engineer will have experience in: Performing full-chip and block-level static timing analysis on complex ASIC and SoC designs. Driving timing closure across all implementation stages, from synthesis through to sign-off. Analysing and resolving setup, hold, clock gating and signal integrity issues. Developing timing constraints and ensuring accurate timing models and methodologies are implemented. Working closely with Physical Design, RTL Design and Verification teams to optimise performance, power and area (PPA). Supporting sign-off activities including STA, timing verification and silicon bring-up readiness. Debugging and resolving complex timing issues within advanced process nodes.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Requirements: A strong academic background in Electronics, Electrical Engineering or a related discipline. Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation. Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC and SoC designs. Strong knowledge of industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler and place-and-route tools. Experience working on complex, high-performance semiconductor products, ideally within AI, HPC or data centre applications. Strong scripting skills using Tcl, Perl or Python to automate timing analysis and improve design methodologies. Excellent communication skills and the ability to work effectively within cross-functional engineering teams.

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This is a fantastic opportunity to join a company with a strong engineering culture, work on technically challenging products and become part of a close-knit team where your contributions will have a direct impact.

For more information on this opportunity, or other Physical Design positions across the UK and Europe, please contact Jordan Browne.

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Skills

Static Timing Analysis
Physical Design
ASIC Implementation
Timing Closure Methodologies
Sign-off Flows
EDA Tools
Synopsys PrimeTime
Design Compiler
Place-and-route Tools
Scripting Skills
Tcl
Perl
Python
Communication Skills
Cross-functional Teams

Location

Cambridgeshire, England, United Kingdom

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