Aion Silicon
Staff Physical Design Engineer
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Staff Physical Design Engineer
Staff Physical Design Engineer
Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Physical Design. With design centres across the UK, Spain, Hyderabad, and Morocco, this opportunity offers the flexibility to be based globally. Click the link below to apply and express your interest.
Purpose of Role
The Staff Physical Design Engineer is a senior-level role within a Physical Implementation Design Team.
- Ownership of block development, with possibility of taking full responsibility from RTL to GDS
- Guaranteed autonomy in own responsibilities while maintaining robustness in execution
- Responsible for managing 2-3 junior engineers, including line management and day-to-day oversight
- Expected to demonstrate ability to mentor and develop talent within the team
Responsibilities
The role requires an experienced Physical Design Engineer with the following key responsibilities:
- Work independently with minimal supervision on complex physical design projects
- Solve moderate to advanced complexity technical problems with sound judgment
- Maintain high quality standards throughout deliverables
- Handle multi-assignment workflows across various teams or customers
- Collaborate with senior team members to resolve challenging design issues
- Demonstrate expertise in key tools, such as:
- Synthesis (Synopsys DC or Cadence Genus)
- Place & Route (PnR) – Synopsys ICC, Cadence Virtuoso EDI, or Mentor Olympus
- Formal verification (e.g., Mentor Formality, Synopsys FormalPro)
- Custom Layout techniques
- Analog simulation
- Chip finishing & extraction
- Contribute to technical white papers and documentation
- Assist in sales support (e.g., Statements of Work – SOW)
- Uphold time management & adherence to deadlines
- Act as a technical leader, mentoring and supervising a small team
- Display strong self-discipline and problem-solving initiative
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Qualifications & Skills
Education & Experience
- Degree, Master’s, or PhD in relevant subject area (e.g., electronics, ECE, EE)
- Minimum of 5+ years’ experience in Physical Design
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Technical Skills & Expertise
- Extensive physical verification experience:
- DRC (Design Rule Checking)
- LVS (Layout vs. Schematic verification)
- Antenna checks
- ERC (Electrical Rule Checking)
- Strong chip development skills across multiple nanometer process nodes:
- 28nm, 22nm, 16nm, 12nm, 7nm, 5nm, 3nm
- Proficiency in STA (Static Timing Analysis)
- Fluency in place, route & optimization tools, such as:
- Synopsys ICC/Digiti (PnR)
- Cadence Genus/SPB/Sounder (Synthesis)
- Mentor Calibre or Synopsys IC Validator (RVE/LVS/DRC)
- Formal verification tools (Mentor Formality, Synopsys FormalPro)
Attribute & Behaviors
- Self-organized, adaptable to changing priorities
- Exceptional team leadership and cross-functional collaboration
- Ability to work under pressure with tight deadlines
- Strong organisation, problem-solving, and analytical mindset
- Highly initiative-driven with minimal supervision
- Attention to detail in deliverables and project execution
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